Every microprocessor Wikipedia’s own transistor-count table lists with a year and a count, 247 chips, 1970–2026. Doubling time: 2.12 years (95% CI [2.05, 2.20], R²=0.915) — excluding both the popular “18 months” folklore and Moore’s own revised “two years” prediction. Split the data at its own median year: the point estimate for a slowdown exists (2.08→2.44 yrs) but the interaction test's CI crosses zero (p=0.16) — the desk can’t confirm Moore’s law itself bent. What does change: R² collapses 0.88→0.35, not because chips stopped getting denser but because “a microprocessor” stopped meaning one thing.
Gordon Moore's 1965 paper predicted the number of components on a chip would double every year; his own 1975 revision, the version that actually stuck, said every two years. Fifty years of retelling compressed that into “doubles every 18 months” (a figure usually credited to Moore but actually an Intel executive's 1975 gloss on cost-per-transistor, not transistor count), and more recently into “Moore's law is dead,” as clock speeds stalled and chipmakers started talking about chiplets and 3D stacking instead of shrinking a single die. This run skips the folklore and fits the actual number: every microprocessor Wikipedia's own transistor-count table lists with a year and a count, 247 chips, 1970–2026.
One row is dropped from the fit before anything else: a 2025 research demonstration (a single transistor built from 3-atom-thick molybdenum disulfide) is not a commercial microprocessor, and its 5,931-transistor count is not comparable to a shipping product — it stays in the raw CSV, excluded here with the reason stated, not silently dropped. 247 chips remain, and because 57 calendar years produced them (as many as 18 in a single year), these are not independent draws from one population any more than the months inside a single presidency were in run 028 — the headline fit below uses year-clustered standard errors for exactly that reason, alongside the plain per-chip OLS for comparison.
The law holds, tightly. Regressing log₂(transistor count) on year: doubling every 2.12 years, 95% CI [2.05, 2.20], R²=0.915, t=56.5 (p underflows double-precision zero). That interval sits entirely above 1.5 years — the “18 months” folklore is excluded, not confirmed — and, more surprising, entirely above 2.0 as well: even Moore's own revised prediction runs a little faster than what 56 years of actual chips did. The commonly cited version overstates the pace; Moore's own number understates it, if only slightly.
Now the “is it dead” question, tested the same mechanical way run 516 tested the marathon “plateau”: split at the data's own median year (2009, not a cherry-picked one) and fit each half. The point estimate does slow down — 2.08 years early to 2.44 years late — but testing the gap directly (one combined regression, an interaction term) puts it at -0.0719 log₂-units/yr, 95% CI [-0.1729, +0.0291], p=0.16. That interval contains zero. The desk cannot confirm Moore's law itself slowed down, on this data, at conventional significance — and won't round a p=0.16 up to a trend because the folklore says it should exist.
What genuinely changes between the two eras isn't the slope; it's how well any single line fits. R² falls from 0.88 early to 0.35 late — a real, large drop, just not the drop the “bending” story expects. The likeliest reason is sitting in the Designer column: the early table is almost entirely single-die CPUs from a handful of firms on a shared node roadmap; the late table mixes mobile SoCs, GPUs, multi-chip server modules, and accelerators with wildly different area, power, and packaging constraints under the same “processor” label. Widening the definition of the thing being measured widens the scatter around its trend line — that is a real change in what “a microprocessor” means, not evidence the underlying manufacturing pace itself slowed.
The most recent window undercuts the “dead” story even on point estimates: the last decade alone (2017–2026, n=76) doubles every 1.87 years (95% CI [1.51, 2.44], R²=0.49) — faster than the late-era half and near the full-period average, not slower. Its own CI is wide enough to overlap both the early and late eras, so it isn't proof of a reacceleration either — only one more honest data point against a claim that gets repeated with far more confidence than the arithmetic supports in either direction.
| Specification | n | doubling time | 95% CI (yrs) | R² | p |
|---|---|---|---|---|---|
| Full period, year-clustered SE | 247 | 2.12 yrs | [2.05, 2.20] | 0.915 | — (underflows; t=56.5) |
| Full period, plain OLS | 247 | 2.12 yrs | [2.05, 2.21] | 0.915 | 4.24e-133 |
| Early era, 1970–2009 | 123 | 2.08 yrs | [1.95, 2.23] | 0.878 | 4.44e-57 |
| Late era, 2009–2026 | 124 | 2.44 yrs | [1.96, 3.24] | 0.346 | 6.91e-13 |
| Recent decade, 2017–2026 | 76 | 1.87 yrs | [1.51, 2.44] | 0.494 | 1.47e-12 |
Interaction test (late slope − early slope, one combined regression, log₂ units/yr): -0.0719, 95% CI [-0.1729, +0.0291], p=0.162 — contains zero.
The full-period year-clustered fit's own p-value underflows double-precision zero (t=56.5 on 56 year-clusters); the plain per-chip OLS row above (p=4.24e-133) is reported instead wherever a finite p is needed for comparison — the two fits agree to four decimal places on the slope itself.
Method. Source: en.wikipedia.org/wiki/Transistor_count, the article’s own “Microprocessors” wikitable, 248 raw rows as published, each already cited in the article to a datasheet, press release, or die-shot analysis. Transistor counts given as ranges (multi-source disagreement on a single chip) are read at their midpoint; footnote markers are stripped; one 2025 row (a single-transistor 2D-material research demonstration, not a shipping product) is excluded from the fit and kept in the raw CSV. The primary fit regresses log₂(transistor count) on release year across every remaining chip, with year-clustered standard errors because multiple chips in the same year are not independent draws. Era splits use the fitted sample’s own median year, mechanically, not a hand-picked inflection point (the same method run 516 used for the marathon record). The interaction test (does the slope itself change) is a single OLS regression of log₂(count) on year, era, and their interaction, so the reported gap and its CI/p come from one model, not two separately eyeballed fits.
Limits, stated plainly. “Transistor count” is not the same quantity Gordon Moore described in 1965 (planar transistors on a single monolithic die) by the end of this series — several of the highest recent counts (AMD’s Epyc and MI300 modules, IBM’s Telum, POWER1/2) are multi-chip modules summed across several dies, which this run does not separate from single-die parts because Wikipedia’s own table doesn’t either; if anything this inflates the recent-era count relative to a strict single-die comparison, working against, not for, the “still healthy” finding above. Clock speed and single-thread performance are a different metric entirely and did plateau in this same period (the end of Dennard scaling, roughly the mid-2000s) — this run says nothing about that claim, only about raw transistor count, and readers who have heard “Moore’s law is dead” are very often hearing a claim about clock speed or IPC, not about this number. Wikipedia’s table is itself a convenience sample of chips someone thought notable enough to add a citation for, not a census of every microprocessor ever shipped — smaller, less-publicized parts are underrepresented, especially in the earliest and most recent years where the table is thinnest (n=1 for 2024, n=0 for 2025 once the excluded research chip is removed, n=1 for 2026).
| Year | Processor | Designer | Transistor count |
|---|---|---|---|
| 1970 | MP944 (20-bit, 6-chip, 28 chips total) | Garrett AiResearch | 74,442 |
| 1971 | Intel 4004 (4-bit, 16-pin) | Intel | 2,250 |
| 1971 | TMX 1795 (8-bit, 24-pin) | Texas Instruments | 3,078 |
| 1972 | Intel 8008 (8-bit, 18-pin) | Intel | 3,500 |
| 1973 | NEC μCOM-4 (4-bit, 42-pin) | NEC | 2,500 |
| 1973 | Toshiba TLCS-12 (12-bit) | Toshiba | 11,000 |
| 1974 | Intel 4040 (4-bit, 16-pin) | Intel | 3,000 |
| 1974 | Motorola 6800 (8-bit, 40-pin) | Motorola | 4,100 |
| 1974 | HP Nanoprocessor (8-bit, 40-pin) | Hewlett-Packard | 4,639 |
| 1974 | Intel 8080 (8-bit, 40-pin) | Intel | 6,000 |
| 1974 | TMS 1000 (4-bit, 28-pin) | Texas Instruments | 8,000 |
| 1975 | Intersil IM6100 (12-bit, 40-pin; clone of PDP-8) | Intersil | 4,000 |
| 1975 | MOS Technology 6502 (8-bit, 40-pin) | MOS Technology | 4,528 |
| 1975 | CDP 1801 (8-bit, 2-chip, 40-pin) | RCA | 5,000 |
| 1976 | Zilog Z80 (8-bit, 4-bit ALU, 40-pin) | Zilog | 8,500 |
| 1976 | TMS9900 (16-bit) | Texas Instruments | 8,000 |
| 1976 | Intel 8085 (8-bit, 40-pin) | Intel | 6,500 |
| 1976 | RCA 1802 (8-bit, 40-pin) | RCA | 5,000 |
| 1977 | Bellmac-8 (8-bit) | Bell Labs | 7,000 |
| 1978 | Motorola 6809 (8-bit with some 16-bit features, 40-pin) | Motorola | 9,000 |
| 1978 | Intel 8086 (16-bit, 40-pin) | Intel | 29,000 |
| 1979 | Zilog Z8000 (16-bit) | Zilog | 17,500 |
| 1979 | Intel 8088 (16-bit, 8-bit data bus) | Intel | 29,000 |
| 1979 | Motorola 68000 (16/32-bit, 32-bit registers, 16-bit ALU) | Motorola | 68,000 |
| 1980 | Intel 8051 (8-bit, 40-pin) | Intel | 50,000 |
| 1981 | WDC 65C02 | WDC | 11,500 |
| 1981 | ROMP (32-bit) | IBM | 45,000 |
| 1982 | Intel 80186 (16-bit, 68-pin) | Intel | 55,000 |
| 1982 | Intel 80286 (16-bit, 68-pin) | Intel | 134,000 |
| 1983 | WDC 65C816 (8/16-bit) | WDC | 22,000 |
| 1984 | Motorola 68020 (32-bit; 114 pins used) | Motorola | 190,000 |
| 1984 | NEC V20 | NEC | 63,000 |
| 1985 | Novix NC4016 (16-bit) | Harris Corporation | 16,000 |
| 1985 | ARM 1 (32-bit; no cache) | Acorn | 25,000 |
| 1985 | Intel 80386 (32-bit, 132-pin; no cache) | Intel | 275,000 |
| 1986 | ARM 2 (32-bit, 84-pin; no cache) | Acorn | 27,000 |
| 1986 | Z80000 (32-bit; very small cache) | Zilog | 91,000 |
| 1986 | SPARC MB86900 (32-bit; no cache) | Fujitsu | 110,000 |
| 1986 | NEC V60[35] (32-bit; no cache) | NEC | 375,000 |
| 1987 | Motorola 68030 (32-bit, very small caches) | Motorola | 273,000 |
| 1987 | NEC V70[35] (32-bit; no cache) | NEC | 385,000 |
| 1987 | TI Explorer's 32-bit Lisp machine chip | Texas Instruments | 553,000 |
| 1987 | Hitachi Gmicro/200[37] | Hitachi | 730,000 |
| 1988 | DEC WRL MultiTitan | DEC WRL | 180,000 |
| 1988 | Intel i960 (32-bit, 33-bit memory subsystem, no cache) | Intel | 250,000 |
| 1989 | Intel 80486 (32-bit, 8 KB cache) | Intel | 1,180,235 |
| 1989 | Intel i860 (32/64-bit, 128-bit SIMD, cache, VLIW) | Intel | 1,000,000 |
| 1989 | Intel i960CA (32-bit, cache) | Intel | 600,000 |
| 1989 | ARM 3 (32-bit, 4 KB cache) | Acorn | 310,000 |
| 1990 | Motorola 68040 (32-bit, 8 KB caches) | Motorola | 1,200,000 |
| 1990 | POWER1 (9-chip module, 72 kB of cache) | IBM | 6,900,000 |
| 1991 | ARM 6 (32-bit, no cache for this 60 variant) | ARM | 35,000 |
| 1991 | R4000 (64-bit, 16 KB of caches) | MIPS | 1,350,000 |
| 1992 | Hitachi SH-1 (32-bit, no cache) | Hitachi | 600,000 |
| 1992 | Intel i960CF (32-bit, cache) | Intel | 900,000 |
| 1992 | Alpha 21064 (64-bit, 290-pin; 16 KB of caches) | DEC | 1,680,000 |
| 1993 | Hitachi HARP-1 (32-bit, cache) | Hitachi | 2,800,000 |
| 1993 | Pentium (32-bit, 16 KB of caches) | Intel | 3,100,000 |
| 1993 | POWER2 (8-chip module, 288 kB of cache) | IBM | 23,037,000 |
| 1994 | PowerPC 601 (32-bit, 32 KB of caches) | Apple, IBM, Motorola | 2,800,000 |
| 1994 | Motorola 68060 (32-bit, 16 KB of caches) | Motorola | 2,500,000 |
| 1994 | PowerPC 603 (32-bit, 16 KB of caches) | Apple, IBM, Motorola | 1,600,000 |
| 1994 | ARM700 (32-bit; 8 KB cache) | ARM | 578,977 |
| 1994 | MuP21 (21-bit,[50] 40-pin; includes video) | Offete Enterprises | 7,000 |
| 1995 | SA-110 (32-bit, 32 KB of caches) | Acorn, DEC, Apple | 2,500,000 |
| 1995 | PowerPC 603e (32-bit, 32 KB of caches) | Apple, IBM, Motorola | 2,600,000 |
| 1995 | PA-8000 64-bit, no cache | HP | 3,800,000 |
| 1995 | Pentium Pro (32-bit, 16 KB of caches;[56] L2 cache on-package, but on separate die) | Intel | 5,500,000 |
| 1995 | Alpha 21164 EV5 (64-bit, 112 kB cache) | DEC | 9,300,000 |
| 1996 | AMD K5 (32-bit, caches) | AMD | 4,300,000 |
| 1996 | Alpha 21164A EV56 (64-bit, 112 kB cache) | DEC | 9,660,000 |
| 1997 | F21 (21-bit; includes e.g. video) | Offete Enterprises | 15,000 |
| 1997 | AVR (8-bit, 40-pin; w/memory) | Nordic VLSI/Atmel | 140,000 |
| 1997 | Pentium II Klamath (32-bit, 64-bit SIMD, caches) | Intel | 7,500,000 |
| 1997 | AMD K6 (32-bit, caches) | AMD | 8,800,000 |
| 1998 | Pentium II Deschutes (32-bit, large cache) | Intel | 7,500,000 |
| 1998 | Alpha 21264 EV6 (64-bit) | DEC | 15,200,000 |
| 1998 | Hitachi SH-4 (32-bit, caches)[62] | Hitachi | 3,200,000 |
| 1998 | Alpha 21164PC PCA57 (64-bit, 48 kB cache) | Samsung | 5,700,000 |
| 1999 | ARM 9TDMI (32-bit, no cache) | Acorn | 111,000 |
| 1999 | Pentium III Katmai (32-bit, 128-bit SIMD, caches) | Intel | 9,500,000 |
| 1999 | Emotion Engine (64-bit, 128-bit SIMD, cache) | Sony, Toshiba | 12,000,000 |
| 1999 | AMD K6-III (32-bit, caches) | AMD | 21,300,000 |
| 1999 | AMD K7 (32-bit, caches) | AMD | 22,000,000 |
| 1999 | Pentium II Mobile Dixon (32-bit, caches) | Intel | 27,400,000 |
| 2000 | Pentium 4 Willamette (32-bit, large cache) | Intel | 42,000,000 |
| 2000 | Gekko (32-bit, large cache) | IBM, Nintendo | 21,000,000 |
| 2000 | Pentium III Coppermine (32-bit, large cache) | Intel | 21,000,000 |
| 2001 | Pentium III Tualatin (32-bit, large cache) | Intel | 45,000,000 |
| 2001 | SPARC64 V (64-bit, large cache) | Fujitsu | 191,000,000 |
| 2002 | Pentium 4 Northwood (32-bit, large cache) | Intel | 55,000,000 |
| 2002 | Itanium 2 McKinley (64-bit, large cache) | Intel | 220,000,000 |
| 2003 | Alpha 21364 (64-bit, 946-pin, SIMD, very large caches) | DEC | 152,000,000 |
| 2003 | Itanium 2 Madison 6M (64-bit) | Intel | 410,000,000 |
| 2003 | AMD K8 (64-bit, large cache) | AMD | 105,900,000 |
| 2003 | PlayStation 2 single chip (CPU + GPU) | Sony, Toshiba | 53,500,000 |
| 2003 | AMD K7 Barton (32-bit, large cache) | AMD | 54,300,000 |
| 2003 | Pentium M Banias (32-bit) | Intel | 77,000,000 |
| 2004 | Pentium 4 Prescott (32-bit, large cache) | Intel | 112,000,000 |
| 2004 | Pentium M Dothan (32-bit) | Intel | 144,000,000 |
| 2004 | SPARC64 V+ (64-bit, large cache) | Fujitsu | 400,000,000 |
| 2004 | Itanium 2 (64-bit;9 MB cache) | Intel | 592,000,000 |
| 2005 | Xenon (64-bit, 128-bit SIMD, large cache) | IBM | 165,000,000 |
| 2005 | Pentium 4 Prescott-2M (32-bit, large cache) | Intel | 169,000,000 |
| 2005 | Pentium D Smithfield (64-bit, large cache) | Intel | 228,000,000 |
| 2005 | Cell (32-bit, cache) | Sony, IBM, Toshiba | 250,000,000 |
| 2006 | Pentium D Presler (64-bit, large cache) | Intel | 362,000,000 |
| 2006 | Dual-core Itanium 2 (64-bit, SIMD, large caches) | Intel | 1,700,000,000 |
| 2006 | Pentium 4 Cedar Mill (32-bit, large cache) | Intel | 184,000,000 |
| 2006 | Core 2 Duo Conroe (dual-core 64-bit, large caches) | Intel | 291,000,000 |
| 2007 | ARM Cortex-A9 (32-bit, (optional) SIMD, caches) | ARM | 26,000,000 |
| 2007 | Core 2 Duo Allendale (dual-core 64-bit, SIMD, large caches) | Intel | 169,000,000 |
| 2007 | Uniphier | Matsushita | 250,000,000 |
| 2007 | Core 2 Duo Wolfdale (dual-core 64-bit, SIMD, caches) | Intel | 411,000,000 |
| 2007 | AMD K10 quad-core 2M L3 (64-bit, large caches) | AMD | 463,000,000 |
| 2007 | SPARC64 VI (64-bit, SIMD, large caches) | Fujitsu | 540,000,000 |
| 2007 | POWER6 (64-bit, large caches) | IBM | 789,000,000 |
| 2008 | Six-core Xeon 7400 (64-bit, SIMD, large caches) | Intel | 1,900,000,000 |
| 2008 | Atom (32-bit, large cache) | Intel | 47,000,000 |
| 2008 | Core 2 Duo Wolfdale 3M (dual-core 64-bit, SIMD, large caches) | Intel | 230,000,000 |
| 2008 | SPARC64 VII (64-bit, SIMD, large caches) | Fujitsu | 600,000,000 |
| 2008 | Core i7 (quad-core 64-bit, SIMD, large caches) | Intel | 731,000,000 |
| 2008 | AMD K10 quad-core 6M L3 (64-bit, SIMD, large caches) | AMD | 758,000,000 |
| 2009 | Six-core Opteron 2400 (64-bit, SIMD, large caches) | AMD | 904,000,000 |
| 2009 | SPARC64 VIIIfx (64-bit, SIMD, large caches) | Fujitsu | 760,000,000 |
| 2010 | Atom (Pineview) 64-bit, 1-core, 512 kB L2 cache | Intel | 123,000,000 |
| 2010 | Atom (Pineview) 64-bit, 2-core, 1 MB L2 cache | Intel | 176,000,000 |
| 2010 | SPARC T3 (16-core 64-bit, SIMD, large caches) | Sun/Oracle | 1,000,000,000 |
| 2010 | Six-core Core i7 (Gulftown) | Intel | 1,170,000,000 |
| 2010 | POWER7 32M L3 (8-core 64-bit, SIMD, large caches) | IBM | 1,200,000,000 |
| 2010 | Quad-core z196[89] (64-bit, very large caches) | IBM | 1,400,000,000 |
| 2010 | Quad-core Itanium Tukwila (64-bit, SIMD, large caches) | Intel | 2,000,000,000 |
| 2010 | Xeon Nehalem-EX (8-core 64-bit, SIMD, large caches) | Intel | 2,300,000,000 |
| 2011 | Quad-core + GPU Core i7 (64-bit, SIMD, large caches) | Intel | 1,160,000,000 |
| 2011 | SPARC64 IXfx (64-bit, SIMD, large caches) | Fujitsu | 1,870,000,000 |
| 2011 | Six-core Core i7/8-core Xeon E5 (Sandy Bridge-E/EP) (64-bit, SIMD, large caches) | Intel | 2,270,000,000 |
| 2011 | Xeon Westmere-EX (10-core 64-bit, SIMD, large caches) | Intel | 2,600,000,000 |
| 2012 | Xeon Phi (61-core 32-bit, 512-bit SIMD, caches) | Intel | 5,000,000,000 |
| 2012 | Itanium Poulson (8-core 64-bit, SIMD, caches) | Intel | 3,100,000,000 |
| 2012 | SPARC64 X (64-bit, SIMD, caches) | Fujitsu | 2,990,000,000 |
| 2012 | Six-core zEC12 (64-bit, SIMD, large caches) | IBM | 2,750,000,000 |
| 2012 | AMD Bulldozer (8-core 64-bit, SIMD, caches) | AMD | 1,200,000,000 |
| 2012 | Quad-core + GPU Core i7 Ivy Bridge (64-bit, SIMD, caches) | Intel | 1,400,000,000 |
| 2012 | Quad-core + GPU AMD Trinity (64-bit, SIMD, caches) | AMD | 1,303,000,000 |
| 2012 | Atom "Medfield" (64-bit) | Intel | 432,000,000 |
| 2012 | POWER7+ (8-core 64-bit, SIMD, 80 MB L3 cache) | IBM | 2,100,000,000 |
| 2013 | Apple A7 (dual-core 64/32-bit ARM64, "mobile SoC", SIMD, caches) | Apple | 1,000,000,000 |
| 2013 | Six-core Core i7 Ivy Bridge E (64-bit, SIMD, caches) | Intel | 1,860,000,000 |
| 2013 | POWER8 (12-core 64-bit, SIMD, caches) | IBM | 4,200,000,000 |
| 2013 | Xbox One main SoC (64-bit, SIMD, caches) | Microsoft, AMD | 5,000,000,000 |
| 2014 | Xeon Ivy Bridge-EX (15-core 64-bit, SIMD, caches) | Intel | 4,310,000,000 |
| 2014 | Xeon Haswell-E5 (18-core 64-bit, SIMD, caches) | Intel | 5,560,000,000 |
| 2014 | Apple A8X (tri-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 3,000,000,000 |
| 2014 | Apple A8 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 2,000,000,000 |
| 2014 | Quad-core + GPU Core i7 Haswell (64-bit, SIMD, caches) | Intel | 1,400,000,000 |
| 2014 | Core i7 Haswell-E (8-core 64-bit, SIMD, caches) | Intel | 2,600,000,000 |
| 2015 | SPARC M7 (32-core 64-bit, SIMD, caches) | Oracle | 10,000,000,000 |
| 2015 | Quad-core + GPU GT2 Core i7 Skylake K (64-bit, SIMD, caches) | Intel | 1,750,000,000 |
| 2015 | Dual-core + GPU Iris Core i7 Broadwell-U (64-bit, SIMD, caches) | Intel | 1,900,000,000 |
| 2015 | Apple A9 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 2,000,000,000 |
| 2015 | Apple A9 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 2,000,000,000 |
| 2015 | Apple A9X (dual core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 3,000,000,000 |
| 2015 | IBM z13 (64-bit, caches) | IBM | 3,990,000,000 |
| 2015 | IBM z13 Storage Controller | IBM | 7,100,000,000 |
| 2016 | Xeon Phi (72-core 64-bit, 512-bit SIMD, caches) | Intel | 8,000,000,000 |
| 2016 | Xeon Broadwell-E5 (22-core 64-bit, SIMD, caches) | Intel | 7,200,000,000 |
| 2016 | HiSilicon Kirin 960 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Huawei | 4,000,000,000 |
| 2016 | Core i7 Broadwell-E (10-core 64-bit, SIMD, caches) | Intel | 3,200,000,000 |
| 2016 | Qualcomm Snapdragon 835 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 3,000,000,000 |
| 2016 | Zip CPU (32-bit, for FPGAs) | Gisselquist Technology | 1,286 |
| 2016 | Apple A10 Fusion (quad-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 3,300,000,000 |
| 2017 | Xeon (unspecified) | Intel | 7,100,000,000 |
| 2017 | Xbox One X (Project Scorpio) main SoC (64-bit, SIMD, caches) | Microsoft, AMD | 7,000,000,000 |
| 2017 | Xeon Platinum 8180 (28-core 64-bit, SIMD, caches) | Intel | 8,000,000,000 |
| 2017 | IBM z14 (64-bit, SIMD, caches) | IBM | 6,100,000,000 |
| 2017 | Centriq 2400 (64/32-bit, SIMD, caches) | Qualcomm | 18,000,000,000 |
| 2017 | AMD Epyc (32-core 64-bit, SIMD, caches) | AMD | 19,200,000,000 |
| 2017 | IBM z14 Storage Controller (64-bit) | IBM | 9,700,000,000 |
| 2017 | HiSilicon Kirin 970 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Huawei | 5,500,000,000 |
| 2017 | POWER9 (64-bit, SIMD, caches) | IBM | 8,000,000,000 |
| 2017 | Qualcomm Snapdragon 850 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 5,300,000,000 |
| 2017 | Qualcomm Snapdragon 845 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 5,300,000,000 |
| 2017 | AMD Ryzen 5 1600 Ryzen (64-bit, SIMD, caches) | AMD | 4,800,000,000 |
| 2017 | AMD Zeppelin SoC Ryzen (64-bit, SIMD, caches) | AMD | 4,800,000,000 |
| 2017 | Apple A10X Fusion (hexa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 4,300,000,000 |
| 2017 | SPARC64 XII (12-core 64-bit, SIMD, caches) | Fujitsu | 5,450,000,000 |
| 2017 | Apple A11 Bionic (hexa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 4,300,000,000 |
| 2017 | AMD Zen CCX (core complex unit: 4 cores, 8 MB L3 cache) | AMD | 1,400,000,000 |
| 2017 | Freedom U500 Base Platform Chip (E51, 4×U54) RISC-V (64-bit, caches) | SiFive | 250,000,000 |
| 2018 | Apple A12X Bionic (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 10,000,000,000 |
| 2018 | Tegra Xavier SoC (64/32-bit) | Nvidia | 9,000,000,000 |
| 2018 | Fujitsu A64FX (64/32-bit, SIMD, caches) | Fujitsu | 8,786,000,000 |
| 2018 | Qualcomm Snapdragon 8cx / SCX8180 (octa-core ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 8,500,000,000 |
| 2018 | HiSilicon Kirin 980 (octa-core ARM64 "mobile SoC", SIMD, caches) | Huawei | 6,900,000,000 |
| 2018 | Apple A12 Bionic (hexa-core ARM64 "mobile SoC", SIMD, caches) | Apple | 6,900,000,000 |
| 2018 | Qualcomm Snapdragon 855 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 6,700,000,000 |
| 2018 | HiSilicon Kirin 710 (octa-core ARM64 "mobile SoC", SIMD, caches) | Huawei | 5,500,000,000 |
| 2019 | AMD Epyc Rome (64-bit, SIMD, caches) | AMD | 39,540,000,000 |
| 2019 | AWS Graviton2 (64-bit, 64-core ARM-based, SIMD, caches)[144][145] | Amazon | 30,000,000,000 |
| 2019 | IBM z15 SC chip (960 MB L4 cache) | IBM | 12,200,000,000 |
| 2019 | Qualcomm Snapdragon 865 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 10,300,000,000 |
| 2019 | HiSilicon Kirin 990 5G | Huawei | 10,300,000,000 |
| 2019 | AMD Ryzen 9 3900X (64-bit, SIMD, caches, I/O die) | AMD | 9,890,000,000 |
| 2019 | AMD Zen 2 Renoir die | AMD | 9,800,000,000 |
| 2019 | IBM z15 CP chip (12 cores, 256 MB L3 cache) | IBM | 9,200,000,000 |
| 2019 | AMD Zen 2 core (0.5 MB L2 + 4 MB L3 cache) | AMD | 475,000,000 |
| 2019 | AMD Zen 2 server I/O die | AMD | 8,340,000,000 |
| 2019 | HiSilicon Kirin 990 4G | Huawei | 8,000,000,000 |
| 2019 | AMD Ryzen 7 3700X (64-bit, SIMD, caches, I/O die) | AMD | 5,990,000,000 |
| 2019 | AMD Zen 2 CCD (core complex die: 8 cores, 32 MB L3 cache) | AMD | 3,800,000,000 |
| 2019 | AMD Zen 2 client I/O die | AMD | 2,090,000,000 |
| 2019 | AMD Zen 2 CCX (core complex: 4 cores, 16 MB L3 cache) | AMD | 1,900,000,000 |
| 2019 | Apple A13 (hexa-core 64-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 8,500,000,000 |
| 2020 | HiSilicon Kirin 9000 | Huawei | 15,300,000,000 |
| 2020 | Apple M1 (octa-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 16,000,000,000 |
| 2020 | Apple A14 Bionic (hexa-core 64-bit ARM64 "mobile SoC", SIMD, caches) | Apple | 11,800,000,000 |
| 2020 | TI Jacinto TDA4VM (ARM A72, DSP, SRAM) | Texas Instruments | 3,500,000,000 |
| 2020 | AMD Zen 3 CCX (core complex unit: 8 cores, 32 MB L3 cache) | AMD | 4,080,000,000 |
| 2020 | AMD Zen 3 CCD (core complex die) | AMD | 4,150,000,000 |
| 2021 | Core 11th gen Rocket Lake (8-core 64-bit, SIMD, large caches) | Intel | 6,000,000,000 |
| 2021 | AMD Ryzen 7 5800H (64-bit, SIMD, caches, I/O and GPU) | AMD | 10,700,000,000 |
| 2021 | Apple A15 | Apple | 15,000,000,000 |
| 2021 | Dimensity 9000 (ARM64 SoC) | Mediatek | 15,300,000,000 |
| 2021 | Apple M1 Pro (10-core, 64-bit) | Apple | 33,700,000,000 |
| 2021 | Power10 dual-chip module (30 SMT8 cores or 60 SMT4 cores) | IBM | 36,000,000,000 |
| 2021 | Apple M1 Max (10-core, 64-bit) | Apple | 57,000,000,000 |
| 2022 | Apple M1 Ultra (dual-chip module, 2×10 cores) | Apple | 114,000,000,000 |
| 2022 | AMD EPYC Genoa (4th gen/9004 series) 13-chip module (up to 96 cores and 384 MB (L3) + 96 MB (L2) cache)[180] | AMD | 90,000,000,000 |
| 2022 | AMD Epyc 7773X (Milan-X) (multi-chip module, 64 cores, 768 MB L3 cache) | AMD | 26,000,000,000 |
| 2022 | IBM Telum dual-chip module (2×8 cores, 2×256 MB cache) | IBM | 45,000,000,000 |
| 2022 | Dimensity 9200 (ARM64 SoC) | Mediatek | 17,000,000,000 |
| 2022 | Qualcomm Snapdragon 8 Gen 2 (octa-core ARM64 "mobile SoC", SIMD, caches) | Qualcomm | 16,000,000,000 |
| 2022 | Apple A16 (ARM64 SoC) | Apple | 16,000,000,000 |
| 2022 | Apple M2 (octa-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 20,000,000,000 |
| 2023 | AMD Instinct MI300A (multi-chip module, 24 cores, 128 GB GPU memory + 256 MB (LLC/L3) cache) | AMD | 146,000,000,000 |
| 2023 | Apple M2 Ultra (two M2 Max dies) | Apple | 134,000,000,000 |
| 2023 | Apple M3 Max (16-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 92,000,000,000 |
| 2023 | AMD Epyc Bergamo (4th gen/97X4 series) 9-chip module (up to 128 cores and 256 MB (L3) + 128 MB (L2) cache) | AMD | 82,000,000,000 |
| 2023 | Apple M2 Max (12-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 67,000,000,000 |
| 2023 | Apple M2 Pro (12-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 40,000,000,000 |
| 2023 | Apple M3 Pro (dodeca-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 37,000,000,000 |
| 2023 | Apple M3 (octa-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 25,000,000,000 |
| 2023 | Apple A17 | Apple | 19,000,000,000 |
| 2023 | HiSilicon Kirin 9000s | Huawei | 9,510,000,000 |
| 2023 | Sapphire Rapids quad-chip module (up to 60 cores and 112.5 MB of cache)[189] | Intel | 46,000,000,000 |
| 2024 | Apple M4 (deca-core 64-bit ARM64 SoC, SIMD, caches) | Apple | 28,000,000,000 |
| 2026 | NVIDIA Vera (multi-chip module, 88-cores 64-bit Armv9.2, 176MB L2 + 162MB L3 cache) | Nvidia | 227,000,000,000 |
transistor_counts_518.csv (248 raw rows, including the excluded research-prototype row) · fit output (JSON).