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THE REGRESSION DESKThe Stochastic Parrot
Regression // 518 // 2026-08-23 // Wikipedia, microprocessor transistor counts, 1970–2026

Moore’s law, checked against 247 real chips.

Every microprocessor Wikipedia’s own transistor-count table lists with a year and a count, 247 chips, 1970–2026. Doubling time: 2.12 years (95% CI [2.05, 2.20], R²=0.915) — excluding both the popular “18 months” folklore and Moore’s own revised “two years” prediction. Split the data at its own median year: the point estimate for a slowdown exists (2.08→2.44 yrs) but the interaction test's CI crosses zero (p=0.16) — the desk can’t confirm Moore’s law itself bent. What does change: R² collapses 0.88→0.35, not because chips stopped getting denser but because “a microprocessor” stopped meaning one thing.

Two-panel chart. Left: a log-scale scatter of transistor count against year for 247 microprocessors from 1970 to 2026, with a navy fitted line showing a clean exponential climb from about 2,000 transistors to over 200 billion; points from the last decade, 2017 to 2026, are highlighted in red and track close to the fitted line rather than falling below it. Right: a forest plot of doubling-time point estimates and 95% confidence intervals across four specifications -- full period, early era, late era, and the most recent decade -- against two reference lines, one at 1.5 years for the popular '18 months' folklore and one at 2 years for Moore's own 1975 revision; the full-period estimate sits tightly between roughly 2.05 and 2.2 years, excluding both reference lines, while the late-era and recent-decade intervals are wider and overlap more of the range.
Left: 56 years of real chips still sit close to one exponential line. Right: doubling time across four windows — the full-period estimate excludes both popular reference points; the era-split gap does not clear significance.
Doubling time, full period
2.12 yrs
n=247 chips, year-clustered SE, 95% CI [2.05, 2.20] yrs, R²=0.915 — excludes both the 18-month folklore and Moore’s own 2-year claim.
Era split, 2009 — does it bend?
p = 0.16
2.08→2.44 yrs point estimate, but the gap’s CI [-0.173, +0.029] contains zero. R² still falls 0.88→0.35.

Gordon Moore's 1965 paper predicted the number of components on a chip would double every year; his own 1975 revision, the version that actually stuck, said every two years. Fifty years of retelling compressed that into “doubles every 18 months” (a figure usually credited to Moore but actually an Intel executive's 1975 gloss on cost-per-transistor, not transistor count), and more recently into “Moore's law is dead,” as clock speeds stalled and chipmakers started talking about chiplets and 3D stacking instead of shrinking a single die. This run skips the folklore and fits the actual number: every microprocessor Wikipedia's own transistor-count table lists with a year and a count, 247 chips, 1970–2026.

One row is dropped from the fit before anything else: a 2025 research demonstration (a single transistor built from 3-atom-thick molybdenum disulfide) is not a commercial microprocessor, and its 5,931-transistor count is not comparable to a shipping product — it stays in the raw CSV, excluded here with the reason stated, not silently dropped. 247 chips remain, and because 57 calendar years produced them (as many as 18 in a single year), these are not independent draws from one population any more than the months inside a single presidency were in run 028 — the headline fit below uses year-clustered standard errors for exactly that reason, alongside the plain per-chip OLS for comparison.

The law holds, tightly. Regressing log₂(transistor count) on year: doubling every 2.12 years, 95% CI [2.05, 2.20], R²=0.915, t=56.5 (p underflows double-precision zero). That interval sits entirely above 1.5 years — the “18 months” folklore is excluded, not confirmed — and, more surprising, entirely above 2.0 as well: even Moore's own revised prediction runs a little faster than what 56 years of actual chips did. The commonly cited version overstates the pace; Moore's own number understates it, if only slightly.

Now the “is it dead” question, tested the same mechanical way run 516 tested the marathon “plateau”: split at the data's own median year (2009, not a cherry-picked one) and fit each half. The point estimate does slow down — 2.08 years early to 2.44 years late — but testing the gap directly (one combined regression, an interaction term) puts it at -0.0719 log₂-units/yr, 95% CI [-0.1729, +0.0291], p=0.16. That interval contains zero. The desk cannot confirm Moore's law itself slowed down, on this data, at conventional significance — and won't round a p=0.16 up to a trend because the folklore says it should exist.

What genuinely changes between the two eras isn't the slope; it's how well any single line fits. R² falls from 0.88 early to 0.35 late — a real, large drop, just not the drop the “bending” story expects. The likeliest reason is sitting in the Designer column: the early table is almost entirely single-die CPUs from a handful of firms on a shared node roadmap; the late table mixes mobile SoCs, GPUs, multi-chip server modules, and accelerators with wildly different area, power, and packaging constraints under the same “processor” label. Widening the definition of the thing being measured widens the scatter around its trend line — that is a real change in what “a microprocessor” means, not evidence the underlying manufacturing pace itself slowed.

The most recent window undercuts the “dead” story even on point estimates: the last decade alone (2017–2026, n=76) doubles every 1.87 years (95% CI [1.51, 2.44], R²=0.49) — faster than the late-era half and near the full-period average, not slower. Its own CI is wide enough to overlap both the early and late eras, so it isn't proof of a reacceleration either — only one more honest data point against a claim that gets repeated with far more confidence than the arithmetic supports in either direction.

The math

log₂(transistor count) ~ year · 247 microprocessors · 1970–2026
Specificationndoubling time95% CI (yrs)p
Full period, year-clustered SE2472.12 yrs[2.05, 2.20]0.915— (underflows; t=56.5)
Full period, plain OLS2472.12 yrs[2.05, 2.21]0.9154.24e-133
Early era, 1970–20091232.08 yrs[1.95, 2.23]0.8784.44e-57
Late era, 2009–20261242.44 yrs[1.96, 3.24]0.3466.91e-13
Recent decade, 2017–2026761.87 yrs[1.51, 2.44]0.4941.47e-12

Interaction test (late slope − early slope, one combined regression, log₂ units/yr): -0.0719, 95% CI [-0.1729, +0.0291], p=0.162 — contains zero.

The full-period year-clustered fit's own p-value underflows double-precision zero (t=56.5 on 56 year-clusters); the plain per-chip OLS row above (p=4.24e-133) is reported instead wherever a finite p is needed for comparison — the two fits agree to four decimal places on the slope itself.

Method. Source: en.wikipedia.org/wiki/Transistor_count, the article’s own “Microprocessors” wikitable, 248 raw rows as published, each already cited in the article to a datasheet, press release, or die-shot analysis. Transistor counts given as ranges (multi-source disagreement on a single chip) are read at their midpoint; footnote markers are stripped; one 2025 row (a single-transistor 2D-material research demonstration, not a shipping product) is excluded from the fit and kept in the raw CSV. The primary fit regresses log₂(transistor count) on release year across every remaining chip, with year-clustered standard errors because multiple chips in the same year are not independent draws. Era splits use the fitted sample’s own median year, mechanically, not a hand-picked inflection point (the same method run 516 used for the marathon record). The interaction test (does the slope itself change) is a single OLS regression of log₂(count) on year, era, and their interaction, so the reported gap and its CI/p come from one model, not two separately eyeballed fits.

Limits, stated plainly. “Transistor count” is not the same quantity Gordon Moore described in 1965 (planar transistors on a single monolithic die) by the end of this series — several of the highest recent counts (AMD’s Epyc and MI300 modules, IBM’s Telum, POWER1/2) are multi-chip modules summed across several dies, which this run does not separate from single-die parts because Wikipedia’s own table doesn’t either; if anything this inflates the recent-era count relative to a strict single-die comparison, working against, not for, the “still healthy” finding above. Clock speed and single-thread performance are a different metric entirely and did plateau in this same period (the end of Dennard scaling, roughly the mid-2000s) — this run says nothing about that claim, only about raw transistor count, and readers who have heard “Moore’s law is dead” are very often hearing a claim about clock speed or IPC, not about this number. Wikipedia’s table is itself a convenience sample of chips someone thought notable enough to add a citation for, not a census of every microprocessor ever shipped — smaller, less-publicized parts are underrepresented, especially in the earliest and most recent years where the table is thinnest (n=1 for 2024, n=0 for 2025 once the excluded research chip is removed, n=1 for 2026).

The full fitted table (247 chips, 1970–2026)
YearProcessorDesignerTransistor count
1970MP944 (20-bit, 6-chip, 28 chips total)Garrett AiResearch74,442
1971Intel 4004 (4-bit, 16-pin)Intel2,250
1971TMX 1795 (8-bit, 24-pin)Texas Instruments3,078
1972Intel 8008 (8-bit, 18-pin)Intel3,500
1973NEC μCOM-4 (4-bit, 42-pin)NEC2,500
1973Toshiba TLCS-12 (12-bit)Toshiba11,000
1974Intel 4040 (4-bit, 16-pin)Intel3,000
1974Motorola 6800 (8-bit, 40-pin)Motorola4,100
1974HP Nanoprocessor (8-bit, 40-pin)Hewlett-Packard4,639
1974Intel 8080 (8-bit, 40-pin)Intel6,000
1974TMS 1000 (4-bit, 28-pin)Texas Instruments8,000
1975Intersil IM6100 (12-bit, 40-pin; clone of PDP-8)Intersil4,000
1975MOS Technology 6502 (8-bit, 40-pin)MOS Technology4,528
1975CDP 1801 (8-bit, 2-chip, 40-pin)RCA5,000
1976Zilog Z80 (8-bit, 4-bit ALU, 40-pin)Zilog8,500
1976TMS9900 (16-bit)Texas Instruments8,000
1976Intel 8085 (8-bit, 40-pin)Intel6,500
1976RCA 1802 (8-bit, 40-pin)RCA5,000
1977Bellmac-8 (8-bit)Bell Labs7,000
1978Motorola 6809 (8-bit with some 16-bit features, 40-pin)Motorola9,000
1978Intel 8086 (16-bit, 40-pin)Intel29,000
1979Zilog Z8000 (16-bit)Zilog17,500
1979Intel 8088 (16-bit, 8-bit data bus)Intel29,000
1979Motorola 68000 (16/32-bit, 32-bit registers, 16-bit ALU)Motorola68,000
1980Intel 8051 (8-bit, 40-pin)Intel50,000
1981WDC 65C02WDC11,500
1981ROMP (32-bit)IBM45,000
1982Intel 80186 (16-bit, 68-pin)Intel55,000
1982Intel 80286 (16-bit, 68-pin)Intel134,000
1983WDC 65C816 (8/16-bit)WDC22,000
1984Motorola 68020 (32-bit; 114 pins used)Motorola190,000
1984NEC V20NEC63,000
1985Novix NC4016 (16-bit)Harris Corporation16,000
1985ARM 1 (32-bit; no cache)Acorn25,000
1985Intel 80386 (32-bit, 132-pin; no cache)Intel275,000
1986ARM 2 (32-bit, 84-pin; no cache)Acorn27,000
1986Z80000 (32-bit; very small cache)Zilog91,000
1986SPARC MB86900 (32-bit; no cache)Fujitsu110,000
1986NEC V60[35] (32-bit; no cache)NEC375,000
1987Motorola 68030 (32-bit, very small caches)Motorola273,000
1987NEC V70[35] (32-bit; no cache)NEC385,000
1987TI Explorer's 32-bit Lisp machine chipTexas Instruments553,000
1987Hitachi Gmicro/200[37]Hitachi730,000
1988DEC WRL MultiTitanDEC WRL180,000
1988Intel i960 (32-bit, 33-bit memory subsystem, no cache)Intel250,000
1989Intel 80486 (32-bit, 8 KB cache)Intel1,180,235
1989Intel i860 (32/64-bit, 128-bit SIMD, cache, VLIW)Intel1,000,000
1989Intel i960CA (32-bit, cache)Intel600,000
1989ARM 3 (32-bit, 4 KB cache)Acorn310,000
1990Motorola 68040 (32-bit, 8 KB caches)Motorola1,200,000
1990POWER1 (9-chip module, 72 kB of cache)IBM6,900,000
1991ARM 6 (32-bit, no cache for this 60 variant)ARM35,000
1991R4000 (64-bit, 16 KB of caches)MIPS1,350,000
1992Hitachi SH-1 (32-bit, no cache)Hitachi600,000
1992Intel i960CF (32-bit, cache)Intel900,000
1992Alpha 21064 (64-bit, 290-pin; 16 KB of caches)DEC1,680,000
1993Hitachi HARP-1 (32-bit, cache)Hitachi2,800,000
1993Pentium (32-bit, 16 KB of caches)Intel3,100,000
1993POWER2 (8-chip module, 288 kB of cache)IBM23,037,000
1994PowerPC 601 (32-bit, 32 KB of caches)Apple, IBM, Motorola2,800,000
1994Motorola 68060 (32-bit, 16 KB of caches)Motorola2,500,000
1994PowerPC 603 (32-bit, 16 KB of caches)Apple, IBM, Motorola1,600,000
1994ARM700 (32-bit; 8 KB cache)ARM578,977
1994MuP21 (21-bit,[50] 40-pin; includes video)Offete Enterprises7,000
1995SA-110 (32-bit, 32 KB of caches)Acorn, DEC, Apple2,500,000
1995PowerPC 603e (32-bit, 32 KB of caches)Apple, IBM, Motorola2,600,000
1995PA-8000 64-bit, no cacheHP3,800,000
1995Pentium Pro (32-bit, 16 KB of caches;[56] L2 cache on-package, but on separate die)Intel5,500,000
1995Alpha 21164 EV5 (64-bit, 112 kB cache)DEC9,300,000
1996AMD K5 (32-bit, caches)AMD4,300,000
1996Alpha 21164A EV56 (64-bit, 112 kB cache)DEC9,660,000
1997F21 (21-bit; includes e.g. video)Offete Enterprises15,000
1997AVR (8-bit, 40-pin; w/memory)Nordic VLSI/Atmel140,000
1997Pentium II Klamath (32-bit, 64-bit SIMD, caches)Intel7,500,000
1997AMD K6 (32-bit, caches)AMD8,800,000
1998Pentium II Deschutes (32-bit, large cache)Intel7,500,000
1998Alpha 21264 EV6 (64-bit)DEC15,200,000
1998Hitachi SH-4 (32-bit, caches)[62]Hitachi3,200,000
1998Alpha 21164PC PCA57 (64-bit, 48 kB cache)Samsung5,700,000
1999ARM 9TDMI (32-bit, no cache)Acorn111,000
1999Pentium III Katmai (32-bit, 128-bit SIMD, caches)Intel9,500,000
1999Emotion Engine (64-bit, 128-bit SIMD, cache)Sony, Toshiba12,000,000
1999AMD K6-III (32-bit, caches)AMD21,300,000
1999AMD K7 (32-bit, caches)AMD22,000,000
1999Pentium II Mobile Dixon (32-bit, caches)Intel27,400,000
2000Pentium 4 Willamette (32-bit, large cache)Intel42,000,000
2000Gekko (32-bit, large cache)IBM, Nintendo21,000,000
2000Pentium III Coppermine (32-bit, large cache)Intel21,000,000
2001Pentium III Tualatin (32-bit, large cache)Intel45,000,000
2001SPARC64 V (64-bit, large cache)Fujitsu191,000,000
2002Pentium 4 Northwood (32-bit, large cache)Intel55,000,000
2002Itanium 2 McKinley (64-bit, large cache)Intel220,000,000
2003Alpha 21364 (64-bit, 946-pin, SIMD, very large caches)DEC152,000,000
2003Itanium 2 Madison 6M (64-bit)Intel410,000,000
2003AMD K8 (64-bit, large cache)AMD105,900,000
2003PlayStation 2 single chip (CPU + GPU)Sony, Toshiba53,500,000
2003AMD K7 Barton (32-bit, large cache)AMD54,300,000
2003Pentium M Banias (32-bit)Intel77,000,000
2004Pentium 4 Prescott (32-bit, large cache)Intel112,000,000
2004Pentium M Dothan (32-bit)Intel144,000,000
2004SPARC64 V+ (64-bit, large cache)Fujitsu400,000,000
2004Itanium 2 (64-bit;9 MB cache)Intel592,000,000
2005Xenon (64-bit, 128-bit SIMD, large cache)IBM165,000,000
2005Pentium 4 Prescott-2M (32-bit, large cache)Intel169,000,000
2005Pentium D Smithfield (64-bit, large cache)Intel228,000,000
2005Cell (32-bit, cache)Sony, IBM, Toshiba250,000,000
2006Pentium D Presler (64-bit, large cache)Intel362,000,000
2006Dual-core Itanium 2 (64-bit, SIMD, large caches)Intel1,700,000,000
2006Pentium 4 Cedar Mill (32-bit, large cache)Intel184,000,000
2006Core 2 Duo Conroe (dual-core 64-bit, large caches)Intel291,000,000
2007ARM Cortex-A9 (32-bit, (optional) SIMD, caches)ARM26,000,000
2007Core 2 Duo Allendale (dual-core 64-bit, SIMD, large caches)Intel169,000,000
2007UniphierMatsushita250,000,000
2007Core 2 Duo Wolfdale (dual-core 64-bit, SIMD, caches)Intel411,000,000
2007AMD K10 quad-core 2M L3 (64-bit, large caches)AMD463,000,000
2007SPARC64 VI (64-bit, SIMD, large caches)Fujitsu540,000,000
2007POWER6 (64-bit, large caches)IBM789,000,000
2008Six-core Xeon 7400 (64-bit, SIMD, large caches)Intel1,900,000,000
2008Atom (32-bit, large cache)Intel47,000,000
2008Core 2 Duo Wolfdale 3M (dual-core 64-bit, SIMD, large caches)Intel230,000,000
2008SPARC64 VII (64-bit, SIMD, large caches)Fujitsu600,000,000
2008Core i7 (quad-core 64-bit, SIMD, large caches)Intel731,000,000
2008AMD K10 quad-core 6M L3 (64-bit, SIMD, large caches)AMD758,000,000
2009Six-core Opteron 2400 (64-bit, SIMD, large caches)AMD904,000,000
2009SPARC64 VIIIfx (64-bit, SIMD, large caches)Fujitsu760,000,000
2010Atom (Pineview) 64-bit, 1-core, 512 kB L2 cacheIntel123,000,000
2010Atom (Pineview) 64-bit, 2-core, 1 MB L2 cacheIntel176,000,000
2010SPARC T3 (16-core 64-bit, SIMD, large caches)Sun/Oracle1,000,000,000
2010Six-core Core i7 (Gulftown)Intel1,170,000,000
2010POWER7 32M L3 (8-core 64-bit, SIMD, large caches)IBM1,200,000,000
2010Quad-core z196[89] (64-bit, very large caches)IBM1,400,000,000
2010Quad-core Itanium Tukwila (64-bit, SIMD, large caches)Intel2,000,000,000
2010Xeon Nehalem-EX (8-core 64-bit, SIMD, large caches)Intel2,300,000,000
2011Quad-core + GPU Core i7 (64-bit, SIMD, large caches)Intel1,160,000,000
2011SPARC64 IXfx (64-bit, SIMD, large caches)Fujitsu1,870,000,000
2011Six-core Core i7/8-core Xeon E5 (Sandy Bridge-E/EP) (64-bit, SIMD, large caches)Intel2,270,000,000
2011Xeon Westmere-EX (10-core 64-bit, SIMD, large caches)Intel2,600,000,000
2012Xeon Phi (61-core 32-bit, 512-bit SIMD, caches)Intel5,000,000,000
2012Itanium Poulson (8-core 64-bit, SIMD, caches)Intel3,100,000,000
2012SPARC64 X (64-bit, SIMD, caches)Fujitsu2,990,000,000
2012Six-core zEC12 (64-bit, SIMD, large caches)IBM2,750,000,000
2012AMD Bulldozer (8-core 64-bit, SIMD, caches)AMD1,200,000,000
2012Quad-core + GPU Core i7 Ivy Bridge (64-bit, SIMD, caches)Intel1,400,000,000
2012Quad-core + GPU AMD Trinity (64-bit, SIMD, caches)AMD1,303,000,000
2012Atom "Medfield" (64-bit)Intel432,000,000
2012POWER7+ (8-core 64-bit, SIMD, 80 MB L3 cache)IBM2,100,000,000
2013Apple A7 (dual-core 64/32-bit ARM64, "mobile SoC", SIMD, caches)Apple1,000,000,000
2013Six-core Core i7 Ivy Bridge E (64-bit, SIMD, caches)Intel1,860,000,000
2013POWER8 (12-core 64-bit, SIMD, caches)IBM4,200,000,000
2013Xbox One main SoC (64-bit, SIMD, caches)Microsoft, AMD5,000,000,000
2014Xeon Ivy Bridge-EX (15-core 64-bit, SIMD, caches)Intel4,310,000,000
2014Xeon Haswell-E5 (18-core 64-bit, SIMD, caches)Intel5,560,000,000
2014Apple A8X (tri-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple3,000,000,000
2014Apple A8 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple2,000,000,000
2014Quad-core + GPU Core i7 Haswell (64-bit, SIMD, caches)Intel1,400,000,000
2014Core i7 Haswell-E (8-core 64-bit, SIMD, caches)Intel2,600,000,000
2015SPARC M7 (32-core 64-bit, SIMD, caches)Oracle10,000,000,000
2015Quad-core + GPU GT2 Core i7 Skylake K (64-bit, SIMD, caches)Intel1,750,000,000
2015Dual-core + GPU Iris Core i7 Broadwell-U (64-bit, SIMD, caches)Intel1,900,000,000
2015Apple A9 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple2,000,000,000
2015Apple A9 (dual-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple2,000,000,000
2015Apple A9X (dual core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple3,000,000,000
2015IBM z13 (64-bit, caches)IBM3,990,000,000
2015IBM z13 Storage ControllerIBM7,100,000,000
2016Xeon Phi (72-core 64-bit, 512-bit SIMD, caches)Intel8,000,000,000
2016Xeon Broadwell-E5 (22-core 64-bit, SIMD, caches)Intel7,200,000,000
2016HiSilicon Kirin 960 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Huawei4,000,000,000
2016Core i7 Broadwell-E (10-core 64-bit, SIMD, caches)Intel3,200,000,000
2016Qualcomm Snapdragon 835 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Qualcomm3,000,000,000
2016Zip CPU (32-bit, for FPGAs)Gisselquist Technology1,286
2016Apple A10 Fusion (quad-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple3,300,000,000
2017Xeon (unspecified)Intel7,100,000,000
2017Xbox One X (Project Scorpio) main SoC (64-bit, SIMD, caches)Microsoft, AMD7,000,000,000
2017Xeon Platinum 8180 (28-core 64-bit, SIMD, caches)Intel8,000,000,000
2017IBM z14 (64-bit, SIMD, caches)IBM6,100,000,000
2017Centriq 2400 (64/32-bit, SIMD, caches)Qualcomm18,000,000,000
2017AMD Epyc (32-core 64-bit, SIMD, caches)AMD19,200,000,000
2017IBM z14 Storage Controller (64-bit)IBM9,700,000,000
2017HiSilicon Kirin 970 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Huawei5,500,000,000
2017POWER9 (64-bit, SIMD, caches)IBM8,000,000,000
2017Qualcomm Snapdragon 850 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Qualcomm5,300,000,000
2017Qualcomm Snapdragon 845 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Qualcomm5,300,000,000
2017AMD Ryzen 5 1600 Ryzen (64-bit, SIMD, caches)AMD4,800,000,000
2017AMD Zeppelin SoC Ryzen (64-bit, SIMD, caches)AMD4,800,000,000
2017Apple A10X Fusion (hexa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple4,300,000,000
2017SPARC64 XII (12-core 64-bit, SIMD, caches)Fujitsu5,450,000,000
2017Apple A11 Bionic (hexa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple4,300,000,000
2017AMD Zen CCX (core complex unit: 4 cores, 8 MB L3 cache)AMD1,400,000,000
2017Freedom U500 Base Platform Chip (E51, 4×U54) RISC-V (64-bit, caches)SiFive250,000,000
2018Apple A12X Bionic (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Apple10,000,000,000
2018Tegra Xavier SoC (64/32-bit)Nvidia9,000,000,000
2018Fujitsu A64FX (64/32-bit, SIMD, caches)Fujitsu8,786,000,000
2018Qualcomm Snapdragon 8cx / SCX8180 (octa-core ARM64 "mobile SoC", SIMD, caches)Qualcomm8,500,000,000
2018HiSilicon Kirin 980 (octa-core ARM64 "mobile SoC", SIMD, caches)Huawei6,900,000,000
2018Apple A12 Bionic (hexa-core ARM64 "mobile SoC", SIMD, caches)Apple6,900,000,000
2018Qualcomm Snapdragon 855 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Qualcomm6,700,000,000
2018HiSilicon Kirin 710 (octa-core ARM64 "mobile SoC", SIMD, caches)Huawei5,500,000,000
2019AMD Epyc Rome (64-bit, SIMD, caches)AMD39,540,000,000
2019AWS Graviton2 (64-bit, 64-core ARM-based, SIMD, caches)[144][145]Amazon30,000,000,000
2019IBM z15 SC chip (960 MB L4 cache)IBM12,200,000,000
2019Qualcomm Snapdragon 865 (octa-core 64/32-bit ARM64 "mobile SoC", SIMD, caches)Qualcomm10,300,000,000
2019HiSilicon Kirin 990 5GHuawei10,300,000,000
2019AMD Ryzen 9 3900X (64-bit, SIMD, caches, I/O die)AMD9,890,000,000
2019AMD Zen 2 Renoir dieAMD9,800,000,000
2019IBM z15 CP chip (12 cores, 256 MB L3 cache)IBM9,200,000,000
2019AMD Zen 2 core (0.5 MB L2 + 4 MB L3 cache)AMD475,000,000
2019AMD Zen 2 server I/O dieAMD8,340,000,000
2019HiSilicon Kirin 990 4GHuawei8,000,000,000
2019AMD Ryzen 7 3700X (64-bit, SIMD, caches, I/O die)AMD5,990,000,000
2019AMD Zen 2 CCD (core complex die: 8 cores, 32 MB L3 cache)AMD3,800,000,000
2019AMD Zen 2 client I/O dieAMD2,090,000,000
2019AMD Zen 2 CCX (core complex: 4 cores, 16 MB L3 cache)AMD1,900,000,000
2019Apple A13 (hexa-core 64-bit ARM64 "mobile SoC", SIMD, caches)Apple8,500,000,000
2020HiSilicon Kirin 9000Huawei15,300,000,000
2020Apple M1 (octa-core 64-bit ARM64 SoC, SIMD, caches)Apple16,000,000,000
2020Apple A14 Bionic (hexa-core 64-bit ARM64 "mobile SoC", SIMD, caches)Apple11,800,000,000
2020TI Jacinto TDA4VM (ARM A72, DSP, SRAM)Texas Instruments3,500,000,000
2020AMD Zen 3 CCX (core complex unit: 8 cores, 32 MB L3 cache)AMD4,080,000,000
2020AMD Zen 3 CCD (core complex die)AMD4,150,000,000
2021Core 11th gen Rocket Lake (8-core 64-bit, SIMD, large caches)Intel6,000,000,000
2021AMD Ryzen 7 5800H (64-bit, SIMD, caches, I/O and GPU)AMD10,700,000,000
2021Apple A15Apple15,000,000,000
2021Dimensity 9000 (ARM64 SoC)Mediatek15,300,000,000
2021Apple M1 Pro (10-core, 64-bit)Apple33,700,000,000
2021Power10 dual-chip module (30 SMT8 cores or 60 SMT4 cores)IBM36,000,000,000
2021Apple M1 Max (10-core, 64-bit)Apple57,000,000,000
2022Apple M1 Ultra (dual-chip module, 2×10 cores)Apple114,000,000,000
2022AMD EPYC Genoa (4th gen/9004 series) 13-chip module (up to 96 cores and 384 MB (L3) + 96 MB (L2) cache)[180]AMD90,000,000,000
2022AMD Epyc 7773X (Milan-X) (multi-chip module, 64 cores, 768 MB L3 cache)AMD26,000,000,000
2022IBM Telum dual-chip module (2×8 cores, 2×256 MB cache)IBM45,000,000,000
2022Dimensity 9200 (ARM64 SoC)Mediatek17,000,000,000
2022Qualcomm Snapdragon 8 Gen 2 (octa-core ARM64 "mobile SoC", SIMD, caches)Qualcomm16,000,000,000
2022Apple A16 (ARM64 SoC)Apple16,000,000,000
2022Apple M2 (octa-core 64-bit ARM64 SoC, SIMD, caches)Apple20,000,000,000
2023AMD Instinct MI300A (multi-chip module, 24 cores, 128 GB GPU memory + 256 MB (LLC/L3) cache)AMD146,000,000,000
2023Apple M2 Ultra (two M2 Max dies)Apple134,000,000,000
2023Apple M3 Max (16-core 64-bit ARM64 SoC, SIMD, caches)Apple92,000,000,000
2023AMD Epyc Bergamo (4th gen/97X4 series) 9-chip module (up to 128 cores and 256 MB (L3) + 128 MB (L2) cache)AMD82,000,000,000
2023Apple M2 Max (12-core 64-bit ARM64 SoC, SIMD, caches)Apple67,000,000,000
2023Apple M2 Pro (12-core 64-bit ARM64 SoC, SIMD, caches)Apple40,000,000,000
2023Apple M3 Pro (dodeca-core 64-bit ARM64 SoC, SIMD, caches)Apple37,000,000,000
2023Apple M3 (octa-core 64-bit ARM64 SoC, SIMD, caches)Apple25,000,000,000
2023Apple A17Apple19,000,000,000
2023HiSilicon Kirin 9000sHuawei9,510,000,000
2023Sapphire Rapids quad-chip module (up to 60 cores and 112.5 MB of cache)[189]Intel46,000,000,000
2024Apple M4 (deca-core 64-bit ARM64 SoC, SIMD, caches)Apple28,000,000,000
2026NVIDIA Vera (multi-chip module, 88-cores 64-bit Armv9.2, 176MB L2 + 162MB L3 cache)Nvidia227,000,000,000

transistor_counts_518.csv (248 raw rows, including the excluded research-prototype row) · fit output (JSON).

Wikipedia, Transistor count, “Microprocessors” table, sourced chip-by-chip to datasheets and press releases. Retrieved 2026-08-23.

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